Lithography is an optical patterning process that patterns a material, e.g., photoresist, which is then developed to define a mask for integrated circuit fabrication processes. Reducing feature sizes to be smaller than the wavelength of light used to form the pattern in photoresist is referred to as sub-wavelength lithography. Sub-wavelength lithography presents many challenges to manufacturers trying to maintain the economic scaling of semiconductors postulated by Moore's Law. Double patterning lithography techniques are sub-wavelength techniques that are used to achieve sub 45 nm nodes with presently available manufacturing equipment. A standard single photoresist pattern begins to blur at about 45 nm feature size. With double patterning lithography methods, coarse patterns can be used to define patterns that exceed the resolution limit of the optical lithography tool used to pattern the material being patterned and developed as a mask.
As Moore's law continues to drive performance and integration with smaller circuit features, lithography is pushed to new extremes. For 32 nm node patterning, prospects for new lithography techniques such as extreme ultraviolet (EUV) and immersion ArF (IArF) are unclear. An EUV imaging system is composed of mirrors coated with multilayer structures designed to have high reflectivity at a 13.5 nm wavelength. There are significant technical hurdles to implementation of EUV lithography in terms of mask-blank fabrication, high output power source, resist material, etc. Challenges to production use of IArF include very high-refractive index fluids (to enable NA=1.55˜1.6), and accompanying advances in high-index resists and optical materials.
Conventional immersion lithography is unlikely to take the industry to 32 nm node patterning, while Double Patterning Lithography (DPL) is a primary lithography candidate for that technology node. DPL involves the partitioning of dense circuit patterns into two separate exposures. Decreased pattern density in each exposure improves resolution and depth of focus (DOF). Conventional DPL increases manufacturing cost due to its complex process flows, and overlay control between the two patterning exposures becomes a critical issue.
A concern with conventional DPL is an increased manufacturing cost. Two fundamental factors contribute to DPL cost: (1) complex process flows due to double exposure patterning, and (2) tight overlay control between the two patterning exposures. Prior efforts have sought to address these concerns. Two primary approaches to DPL are the LELE (litho-etch-litho-etch) and self-aligned approaches. The first etch step in LELE is necessary to transfer the pattern of the first resist layer into an underlying hard mask, which is not removed during the second exposure. See, e.g., J. Finders, M. Dusa and S. Hsu, “Double Patterning Lithography: The Bridge Between Low k1 ArF and EUV”, Microlithography World, February 2008. Photoresist is re-coated on the surface of the first process for a second exposure. The second mask, having patterns separated from the first mask. The process completes with the hard mask and resist of second exposure.
In self-aligned DPL and other DPL approaches that incorporate two lithographic exposures with only one etch step, the image formed by the first exposure may interact with the image formed by the second exposure. In self-aligned DPL patterns for the first layer are transferred into the hard mask and then nitride spacers are formed on the sidewalls of the patterns. See, e.g., M. Maenhoudt, J. Versluijs, H. Struyf, J. Van Olmen, and M. Van Hove, “Double Patterning Scheme for Sub-0.25 k1 Single Damascene Structures at NA=0.7538, λ=193 nm”, Proc. SPIE Conf. on Optical Microlithography, 2005, pp. 1508-1518. In typical self-aligned DPL, a spacer is formed by deposition or reaction of the film on the pattern, followed by etching to remove all the film material except for the material on the sidewalls. Then, film materials between spacers produce the patterns for the second layer. A major concern of DPL is overlay control, which leads to requirements for more accurate overlay metrology, more representative sampling, reduced model residuals, and improved overlay correction. See, e.g., M. Dusa et al., “Pitch Doubling Through Dual-Patterning Lithography Challenges in Integration and Litho Budgets”, Proc. SPIE Conf. on Optical Microlithography, 2007, pp. 65200G-1-65200G-10.
According to the International Technology Roadmap for Semiconductors, DPL requires overlay control of between 9 nm and 6 nm, which has been a major hurdle for production deployment. A key issue in DPL from the design point of view is the decomposition of the layout for multiple exposures. DPL layout decomposition must satisfy the requirement that two features are assigned opposite colors (corresponding to mask exposures) if their spacing is less than the minimum coloring spacing. Alternate Phase Shift Mask coloring and automatic phase shift conflict detection and resolution methods accomplish layout perturbation, i.e., increasing the spacing between features and increasing the width of critical features, to make the layout-derived graph bipartite. See, A. B. Kahng, S. Vaya and A. Zelikovsky, “New Graph Bipartizations for Double-Exposure, Bright Field Alternating Phase-Shift Mask Layout”, Proc. Asia and South Pacific Design Automation Conference, 2001, pp. 133-138; C. Chiang, A. B. Kahng, S. Sinha and X. Xu, “Fast and Efficient Phase Conflict Detection and Correction in Standard-Cell Layouts”, Proc. IEEE Intl. Conf. on Computer-Aided Design, 2005, pp. 149-156.
However, layout pattern configurations exist in DPL for which features within this minimum coloring spacing cannot all be assigned different colors. In such cases, at least one feature must be split into two or more parts. The Alternate Phase Shift Mask coloring and automatic phase shift conflict detection and resolution methods do not utilize or provide for feature splitting. A drawback of conventional DPL pattern splitting is that it increases manufacturing cost and complexity due to (1) generation of excessive line-ends, which causes yield loss due to overlay error in double-exposure, as well as line-end shortening under defocus; and (2) resulting requirements for tight overlay control, possibly beyond currently envisioned capabilities. Other risks include line edge (CD) errors due to overlay error, and interference mismatch between different masks. Therefore, a key optimization goal is to reduce the total cost of layout decomposition, considering the above-mentioned aspects, as well as other concerns such as forbidden-pitch and other design rule restrictions on each mask, as well as layout density balance across masks.
A major concern of DPL is overlay control, which leads to requirements for more accurate overlay metrology, more representative sampling, reduction in model residuals, and improved overlay correction. Another key issue in DPL from the design point of view is the decomposition of the layout for multiple exposure steps. DPL layout decomposition must satisfy the following requirement: two features must be assigned opposite colors (corresponding to mask exposures) if their spacing is less than the minimum coloring spacing. However, there exist pattern configurations for which features within this minimum coloring spacing cannot all be assigned different colors. In such cases, at least one feature must be split into two or more parts. The feature splitting increases manufacturing cost and complexity due to (1) generation of additional line-ends, which cause yield loss due to overlay error in double-exposure, as well as line-end shortening under defocus; and (2) resulting requirements for tight overlay control, possibly beyond currently envisioned capabilities. Other risks include line edge (CD) errors due to overlay error, and interference mismatch between different masks.